Most integrated circuits (IC's) contain two main regions (1) a core region, which contains most of the IC's functional circuitry and (2) an input/output or I/O region. The I/O region provides the electrical interface between the IC's core region and external circuitry.
Further more, most integrated circuits (IC's) designed today are designed using a library of modular circuit descriptions that are arranged by a circuit designer using an EDA (electronic design automation) tool. These modular circuit descriptions are often referred to as circuit macros or cell macros, because they contain logical and physical descriptions of circuitry and traces that design tools utilizes when preparing for actual IC fabrication. Core regions of I/C's may contain various logic, memory, or processor macros, but a number of those macros may be proprietary or custom designed and additional circuitry may be hand designed, reflecting the highly variable nature of the logic or analog functions of an I/C core. The I/O regions of IC's, however, tend to be much more similar in their function and thus a number of I/O cell libraries have become standardized and are widely used in many different IC designs. Thus, an additional aspect of IC design involves the use of readily available library macro cells and standard design flows for at least parts of most ICs, in particular for I/O regions. Commonly used library cells are readily available from vendors.
The I/O region is frequently called an I/O ring because it contains I/O circuit macros (or cells or modules) that are laterally connected together to form a generally continuous rectangle that is wrapped around the perimeter of the core region. The I/O macro lateral connections are used to efficiently distribute I/O and core power and ground supplies to the I/O macros and thus minimize noise and maximize electrostatic discharge (ESD) protection. The I/O macros contain the interface circuitry for higher supply voltage external signals and for lower supply voltage core signals. I/O macros are typically connected to bond pads that in turn are connected to external pins, leads or solder bumps on the IC's package.
Thus, prior art I/O circuit macros are generally understood as a register descriptor language specification (or the circuit area that the RDL describes) for an I/O region that specifies one or more I/O connections (such as to a bond pad) and lateral connections to other I/O macros used to efficiently distribute I/O and core power and ground supplies and interface circuitry to connect higher supply voltage external signals to lower supply voltage core signals. In typical prior art I/O macros, lateral connections are generally made from I/O macro to I/O macro, while connections transverse or perpendicular to the lateral connections involve I/O signals or power signals going from the I/O region to the IC's core circuitry.
IC costs increase as the IC's area increases, so there is strong motivation to reduce IC area and minimize cost. The area of most IC's is often defined by either the area enclosed by the I/O ring or the area of the core region. When the area bounded by the inside perimeter of the I/O ring, which is related to the number and size of I/O macros, exceeds the area occupied by the IC's core region circuitry, the IC is considered I/O limited or pad limited. In this case the IC would have excess or unused core region area. When the perimeter of core area is larger than the inner perimeter of the I/O ring the IC is considered core limited. In this case the I/O ring would need to be expanded to fit around the core area so there would be excess space in the I/O ring. It follows that IC's with large I/O macro counts and relatively small amounts of core circuitry tend to be I/O limited. IC's with relatively large core areas and relatively low I/O macro counts tend to be core limited. As IC technology has advanced and IC feature sizes shrunk, core circuit density has increased faster than the I/O circuit density. This is generally because the interface and current carrying demands of the I/O circuitry limit the extent to which that circuitry can be miniaturized. As a result, for some time, an increasing percentage of the IC designs have become I/O limited.
Older IC packaging technologies rely on wire bonding to make electrical connections from the I/O macro bond pads to the package pins or leads. I/O macros and their corresponding bond pads are often placed in a rectangular I/O ring around the IC's core since this minimizes bond wire lengths and helps prevent bond wires from crossing. FIG. 1 (Prior Art) shows an example of an IC with a traditional I/O Ring that uses a wire bonded package. I/O rings are also used to distribute core power and ground supplies plus I/O power and ground supplies to the I/O macros in the I/O ring. I/O macros that are attached to bond pads generally contain electrostatic discharge (ESD) diodes that are connected to the I/O power or I/O ground supplies provided by the I/O ring. As the number of ESD diodes tied to the I/O power and I/O ground supplies increases, the IC can handle greater amounts of unwanted static charge, thus increasing the IC's reliability. This need for interconnected ESD diodes provides another strong incentive for IC's to use I/O macros that have I/O ring topologies. Corresponding power and ground supplies are connected together by the I/O ring to help minimize supply related nose thus improving signal quality. The power and ground supplies of the I/O macros placed in the I/O ring normally have lateral connections connected by abutment. For example, I/O power and I/O ground supplies plus core power and core ground rings pass laterally through the I/O macros in a chain-like manner around the entire I/O ring. Individual I/O signals that pass from the bond pads to or from the IC's core typically use the most direct path straight to the IC's core, which is normally transverse or perpendicular to the direction of the I/O ring around the IC's core and normally separated from the lateral connections by being placed in a different vertical layer of the I/C. Placing I/O macros in a peripheral I/O ring also removes I/O macros from the IC's core area, so they don't obstruct core signal routing.
Given the benefits of I/O ring implementations, most I/O macros have been designed to be used in I/O rings. The cost and effort to design I/O macros is significant. As a result, much of the IC design community uses readily available I/O macros that have been optimized for use with I/O ring implementations. This design community acceptance further supports the continued wide use of I/O macros designed to support I/O ring topologies.
I/O Filler Cells
Many I/O rings use I/O filler cells to close gaps between I/O macros that are physically separated. Existing I/O filler cells generally contain fixed lateral connection metal routing stripes that are used to make lateral power and ground supply plus well region and if applicable diffusion region connections between the separated I/O macros. For example if the two I/O macros are 5 um (microns) apart, a 5 um wide I/O filler cell is used to fill the gap between the I/O macros and make the appropriate routing, well region and if applicable diffusion region connections. I/O Filler cells are often available in various sizes for example 1 um wide, 5 um wide, 10 um wide and 50 um wide, and generally have a length that is consistent with their neighboring I/O macros. Most available I/O filler cells have integer micron widths, and I/O macros are usually separated by integer micron distances to facilitate placement of I/O filler cells. For example a 7 um I/O macro to I/O macro separation would be filled by one 5 um filler cell plus two 1 um filler cells. I/O libraries typically include a set of I/O filler cells that are designed to be compatible with the I/O macros in the I/O library. I/O filler cells also include sets of power and ground supply ports that match the physical locations of the corresponding ports on neighboring I/O macros. Most existing I/O filler cells support abutment based I/O ring power and ground lateral connections with metal routing in their upper metal layers.
FIG. 2 (Prior Art) provides a high level example of I/O filler cells connecting together the I/O rings of separated I/O macros. FIG. 3 (Prior Art) provides a detailed example of an I/O filler cell that connects I/O ring segments of two separated I/O macros. Wide I/O filler cells may contain decoupling capacitors that help reduce power and ground noise. Narrow I/O filler cells usually don't have enough room to contain decoupling capacitors and contain simple metal I/O ring routing segments and ports.
Flip Chips and RDL
A newer IC packaging technology, which is called flip chip technology, utilizes solder bumps that are placed on the top of the IC, and these bumps in turn are routed in a Redistribution Layer (RDL layer) to corresponding bond pads in the I/O macros. Because the external signals are connected through transmission elements that run vertically to the I/C, flip chip technology supports I/O macro placements throughout the IC. FIG. 4 (Prior Art) provides an example of redistribution layer routing from bond pads on the IC to solder bumps in a flip-chip design. RDL layers are added to IC's after wafer fabrication and involve wide and thick metal layers typically having well over 100× the cross sectional area of typical signal routes in the underlying IC. It follows that RDL layers are suitable for external I/O related connections, for example between an I/O cell and its' associated soldier bump site, as well as various power and ground connections. RDL layers are unsuitable for signal connections that use relatively small drive transistor such the core logic in most IC's. During Flip chip package assembly the IC is flipped upside down and the solder bumps are physically connected to bump pads in the IC package. These bump pads are in turn connected through the package's substrate layers to soldier balls on the underside of the IC package. FIG. 5 (Prior Art) shows a side view a flip chip IC placed in a flip chip package. Flip chip packages support greater numbers of I/O's than wire bonding packages, and flip chip packages that support 2000+ I/O's are commonly available. Flip chip packages usually have lower electrical parasitics than wire bond packages so they can support higher performances. Due to the use of the redistribution layer and solder bumps, flip chip packaging technology doesn't utilize bond wires, so bond wire crossing limitations and maximum bond wire length limitations aren't relevant. It follows that Flip Chip packages can support I/O macro placement anywhere in the IC's core assuming ESD requirements are met and the I/O macros have access to I/O power and ground supplies plus core power and ground supplies. FIG. 6 (Prior Art) shows an example of an IC that has I/O's scattered throughout its' entire area rather than placing the I/O macros in an I/O ring around the perimeter of the core area. This embodiment has been called an area I/O solution. The I/O macro design and the IC design need to resolve power and ground supply distribution issues along with ESD related interconnection requirements when placing I/O macros in a non-I/O ring topology. Although Flip Chip packages can support flexible I/O macro placement, many IC designs in Flip Chip packages use I/O ring topologies because most I/O macros are designed for I/O ring topologies; I/O rings have efficient proven design flows; and core area routing is more efficient when I/O macros are not placed in the core area. While Flip-Chip packages provide some inherent I/O placement flexibility, Flip Chip designs still flexibility in providing multiple I/O regions.
Short Wide, Tall Thin, and Circuit Under Pad (Cup)
Another key aspect of IC design and packaging involves bond pad implementations. Some core limited designs use short wide I/O macros that are connected to in-line bond pads that have smaller widths than the I/O macros. Some I/O limited designs use tall thin I/O macros that are connected to staggered bond pads, where the bond pads are wider than the I/O macros. In this case the bond pads are placed in two parallel staggered rows for attachment to corresponding I/O macros.
A newer I/O pad technology involves circuit under pad (CUP) implementations where the bond pad is placed on top of the I/O macro. The CUP approach also supports staggered bond pad placement so the bond pads can be wider than the I/O macros. FIG. 7 (Prior Art) shows examples of I/O macros connected to bond pads using: in-line, staggered and CUP implementations. Both Wire Bond and Flip Chip packages support use of in-line, staggered and CUP bond pad implementations. The use of CUP bond pads reduces the size of the I/O region area, because the bond pads do not consume additional placement area outside of the I/O macros. Due to this area saving CUP bond pad embodiments are often preferred. In some unusual cases in-line or staggered bond pads may be over CUP bond pads. For example, some IC processes or I/O macro libraries may not support CUP implementations.